Implementation of DIT FFT Using Area Efficient VLSI Architecture

Authors:R. KIRANMAI, SANA AAFREEN

0802-0805

VLSI Realization of BIST for Low Power Applications

Authors:DURGAPRASAD RATNALA, LOKESH. D

0806-0812

Implementation of CORDIC Algorithm for Low Power Applications

Authors:GURUVILLI GOVINDA RAO, T.RAVI KUMAR

0813-0819

Area Delay Power Efficient Carry Select Adder

Authors:CH. PADMINI RAMYA, CH. SURYA BABU, A .V.S.S.VARMA, G. SATTIBABU

0820-0824

Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation Based ALU Functions

Authors:SHIRISHA KONDURU, SANGEETH KUMAR. B

0820-0825

Implementation of Reliable Priority Encoder Architecture for Matching of Encoded Data

Authors:SHAIK NURJAHAN, H. RAGHUNATHA RAO

0826-0830

Realization of Power Optimized PRPG

Authors:D. RANGANADH, G. S. J. MANI KUMAR

0831-0835

Architecture for a Low-Power Content Addressable Memory Based On Sparse Compression Technique

Authors:NALAM DURGA PRASAD, VISWESWARA RAO P

0836-0845

Performance Analysis and Modelinng of Metallic Plasmonic Nanoantennas for Wireless Optical Communication in Nanonetworks

Authors:SYEDA LUBNA, S. MALATHI

0846-0852

Faults Detection using Parallel Filters Based on Error Correction Codes

Authors:S.M. SHAMSHEER DAULA, G. DIVYAMRUTHA

0853-0856